One current process or method for forming conductive lines or traces in or on an integrated circuit chip package substrate can be described as semi-additive. Such process involves depositing a blanket seed layer of a conductive material on a dielectric layer followed by a patterning of a mask with an opening conductive line or trace. An electrolytic plating process then follows to deposit an electrically conductive material such as copper on the seed layer in the opening in the mask. The mask is then removed as is unwanted seed material to leave the conductive line or trace on the substrate.